The present invention relates to a semiconductor device and a memory access control method and relates to the technology which is useful for a bus master accessing a memory unit after locking a bus, for example.
Patent Literature 1 discloses a memory control circuit which aims at performing the efficient power control of a cache memory by techniques other than the power management performed by an operating system. The memory control circuit counts up a read request counter when a read request from a first-order cache memory to a second-order cache memory is issued, and counts down the read request counter when the second-order cache memory responds to the first-order cache memory, responding to the request. The memory control circuit activates an L2 non-operation counter, when the count value of the read request counter becomes zero. The memory control circuit cuts off the power supply of the L2 cache, when the count value of the L2 non-operation counter exceeds a prescribed value determined in advance.
(Patent Literature 1) Japanese Unexamined Patent Application Publication No. 2015-22330